1. Field of the Invention
The present invention relates to a semiconductor integrated device, and more specifically, to an impedance adjustment circuit of an input circuit used for a high-speed transmission path.
2. Description of Related Art
In a field of a semiconductor integrated device, high-speed communication represented by DDR2 (double data rate 2), for example, has been increasingly employed in communication between semiconductor devices along with an increase of speed in an application set. When such a high-speed communication is employed, there is raised a problem of distortion of transmission signal waveforms caused by signal reflection. This requires impedance matching among an output buffer, a transmission path, and an input buffer. Without impedance matching, an input buffer end which is a receiving end cannot obtain sufficient signal amplitude or overshoot is occurred in a transmission signal, which causes occurrence of noise or distortion of the transmission signal due to reflection. This causes occurrence of error in communication data, which results in communication failure.
Increase in the communication speed causes considerable influence by characteristics of a transmission path on the signal. The influence given by the impedance characteristic on the transmission path cannot be ignored not only in wirings between products but also in fine wirings in a product package (bonding wire, bump (soldering ball), wiring in interposer, for example) or the like. Thus, increasing the accuracy of impedance adjustment circuits has been strongly required.
One example of the impedance control apparatus according to a related art is disclosed in Japanese Unexamined Patent Application Publication No. 2005-061976. Referring now to FIGS. 5 and 6, the impedance control apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2005-061976 will be described.
FIG. 5 shows one example of the structure of the impedance control apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2005-061976. An LSI output signal 202 is output from an LSI 201 which is a semiconductor integrated circuit to be inspected. The LSI output signal 202 is transmitted on an inspection substrate 203 which is an inspection apparatus of the semiconductor integrated circuit such as an LSI tester. A transmission path 204 on the inspection substrate 203 has a characteristic impedance Z0. An output signal from the transmission path 204 is input to an impedance control mechanism 226 of the impedance control apparatus.
A termination resistor (matching means) 205 connected to a termination of the transmission path 204 has impedance that can be varied. An LSI output signal 206 including the reflected wave is taken out from a transmission terminal neighborhood of the transmission path 204 and is connected to an amplitude comparing switch 207 (hereinafter simply referred to as switch 207) to start the amplitude comparison operation. The switch 207 is ON (the switch is closed) in starting the amplitude comparison operation.
An amplitude comparison unit 210 compares the voltage level of an amplitude comparing output signal 208 with the voltage level of an amplitude comparing reference signal 209, and outputs an amplitude comparison signal 211 indicating the comparison result. The amplitude comparing output signal 208 is the LSI output signal 206 including the reflected wave in this example. A resistance controlling clock signal 212 (CLK1) is externally input. A resistance control signal generation unit 213 generates a resistance control signal 214 that controls the resistance component of the impedance of the termination resistor 205 based on the amplitude comparison signal 211 and the resistance controlling clock signal 212 so that the difference between the characteristic impedance of the transmission path 204 and the resistance component of the impedance of the termination resistor 205 is within a certain range.
A phase comparing output signal 215 is a signal that is divided from the amplitude comparing output signal 208, and is the LSI output signal 206 including the reflected wave in this example. The phase comparing output signal 215 is connected to a phase comparing switch 216 (hereinafter simply called switch 216). The switch 216 is ON when the phase comparison operation is started.
A phase comparison unit 221 compares a phase of a phase comparing output signal 218 which passes through a resistor 217 with a phase of a phase comparing reference signal 220 which passes through a resistor 219, and outputs a phase comparison signal 222 indicating the comparison result. A reactance controlling clock signal 223 (CLK2) is externally input. A reactance control signal generation unit 224 generates a reactance control signal 225 that controls reactance component of the impedance of the termination resistor 205 based on the phase comparison signal 222 and the reactance controlling clock signal 223 so that the difference between the characteristic impedance of the transmission path 204 and the reactance component of the impedance of the termination resistor 205 is within a certain range.
FIG. 6 is a diagram showing one example of the structure of a termination resistor (matching means) 205 disclosed in Japanese Unexamined Patent Application Publication No. 2005-061976. A shift resistor 227 to change resistance values of the termination resistor 205 outputs output signals Qr0, Qr1, and Qr2. A signal 228 indicates a reset signal of the shift resistor 227, and a signal 229 indicates output signals of the shift resistor 227.
A shift resistor 231 outputs output signals Qx0, Qx1, and Qx2. A signal 232 indicates a reset signal of the shift resistor 231, and a signal 233 indicates output signals of the shift resistor 231.
A switch 230 is opened or closed according to the output signals 229. The switch 230 changes resistance values of the termination resistor 205. The switch 230 is connected to a terminal a when a potential level of an input signal is Low, and is connected to a terminal b when a potential level of an input signal is High. In summary, the switch 230 is connected to a terminal a when the potential level of the output signals Qr0, Qr1, Qr2 is Low, and is connected to a terminal b when the potential level is High.
A switch 234 is opened or closed according to the output signal 233. The switch 234 changes capacitance values of the termination resistor 205. The switch 234 is OFF (the switch is opened) when a potential level of an input signal is Low, and is ON when a potential level of an input signal is High. In summary, when the potential level of the output signals Qx0, Qx1, and Qx2 is Low, the switches 234 connected to capacitors C0, C1 are OFF, and the switch 234 connected to the capacitor C2 is ON as the output signal Qx2 is input through an inverter 235. When the potential level is High, the switches 234 connected to the capacitors C0, C1 are ON, and the switch 234 connected to the capacitor C2 is OFF.
FIG. 6 shows a case in which the termination resistor 205 is in an initial state. In the initial state, the resistance value of the termination resistor 205 is R2, and the capacitance value is C2. The relation among the resistance values R2, R1, and R0 is R2>R1>R0. The relation among the capacitance values C2, C1, and C0 is C2>C1>C0.
The impedance control mechanism disclosed in Japanese Unexamined Patent Application Publication No. 2005-061976 includes (1) a mechanism that compares the amplitudes of the amplitude comparing reference signal with the LSI output signal including the reflected wave, and controls the resistance component (real part) of the impedance of the termination resistor based on the amplitude comparison result so that the difference of the resistance component between the characteristic impedance of the transmission path and the impedance of the termination resistor (matching means) is within a certain range, and (2) a mechanism that compares the phases of the phase comparing reference signal with the LSI output signal including the reflected wave, and controls the reactance component (imaginary part) of the impedance of the termination resistor based on the phase comparison result so that the difference of the reactance component between the impedance of the termination resistor and the characteristic impedance of the transmission path is within a certain range. In the impedance control mechanism disclosed in Japanese Unexamined Patent Application Publication No. 2005-061976, an input signal is compared with a reference voltage, and a termination resistor is determined using the amplitude of the input signal that is judged, so as to adjust the input impedance.
Other techniques related to the present invention are disclosed in Japanese Unexamined Patent Application Publication No. 2005-229552 and Japanese Unexamined Patent Application Publication No. 2006-203568, disclosing a slew rate control device to prevent malfunction by detecting presence or absence of ringing in output signal waveforms of an output buffer and changing driving ability of drive means according to the detection result.
Further, Japanese Unexamined Patent Application Publication No. 2000-209078 discloses a semiconductor device that enables to suppress ringing occurred in an output signal output from an output circuit when the output signal transits.